About me
I received my PhD from the University of Florida researching low-overhead security solutions for FPGAs. I currently work full time as an Embedded Systems Security researcher and study Reverse Engineering on the side.
- Location:Bay Area, CA
- Age:30
- Nationality:Cuban / American
- Interests:Cyber Physical Security, Embedded Systems, IoT
- Study:University of Florida
- Employment:Embedded Hardware Security Engineer
Education
Bachelors of Science
Studied circuit design and analysis, digital design, software engineering, and analogue circuit design.
Masters of Science
Studied Hardware Security and Trust along with VLSI circuit design.
Doctor of Philosophy
Studied Hardware Security and Trust along with VLSI circuit design.
Work
Pre-Doctoral Fellow/Research Assistant
Graduate Research in the Warren B. Nelms Institute under Dr. Bhunia. Research focuses on Hardware Security and Internet of Things with projects relating to Trojan detection, design validation, IP protection, and logic locking. Also involved in projects relating to the design of self-aware systems, machine learning, electric vehicle charging and implantable/wearable devices.
Hardware Security Research Intern
Performed research involving FPGA PUF, which could reutilize existing reconfigurable elements on the device for reduced overhead. A LUT-level netlist was generated for a design. Half-utilized LUTs were selected and combined with our PUF architecture. Alongside the PUF architecture, a set of tools was developed to insert the PUF into designs and apply FPGA design constraints. Experiments were conducted to analyze PUF performance and stability under a range of different temperatures.
Cyber Security Research Intern
Performed cyber security research that involved designing, developing, and analyzing Physical Unclonable Functions (PUFs). My main responsibilities involved the implementation and analysis of a machine-learning attack on different PUF solutions. Additionally, assisted with the implementation of a PUF hardware solution as well as analyzing the quality and security metrics of the collected data.
Software Engineer Intern/Junior Dev
Development, deployment, and maintenance of RESTful web services for use in Visa and Master Card credit card transactions. Web services were programmed in Java in a test for development style. Along with development, security audits of current using Fortify tools were also performed. Audits aimed to solve log injection issues, prevent leaking sensitive information, ensure proper encryption was used, ect.
Undergraduate Research Assistant
Undergraduate research assistant in the Bio Sensors lab under Dr. Mubarak. Research focuses on automating electrochemical impedance spectroscopy measurements through a multi-electrode device to detect abnormalities in live cells such as cancer.
Projects
Automatic Implementation of Secure Silicon (AISS)
Development of a secure automated System on Chip (SoC) design that scales security measures with the chip design. AISS aims to address four specific attacks, side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. I primarily worked on integrating a PUF for system authentication into the secure security engine design.
SPLIT FPGA PUF
An FPGA based PUF which repurposes existing elements to reduce PUF overhead. Targeting the 6-input look-up table (LUT) architecture present on Xilinx devices the LUT be split in half. The functional logic can occupy one half with the other half utilized as a PUF. This allows for the PUF to be embedded alongside and spread throughout the functional logic.
Memory in Logic PUF
A synthesizable physical unclonable function (PUF) designed for use on FPGAs. Through judicious selection of circuit gates, existing circuit elements can be repurposed to function as a PUF. This allows for the PUF to be distributed throughout the FPGA device.
JTAG IOLock
Modification of the JTAG architecture allowing for encryption of data being sent over I/O pins. The modification allows for transmission encryption keys over secure methods allowing for obfuscation of IC functionality.
Publications
MeLPUF: Memory-in-Logic PUF Structures for Low-Overhead IC Authentication
C. Vega, S. Deb Paul, P. SLPSK, A. Chatterjee, S. Bhunia
Memory in logic physical unclonable function
C. Vega, S. Deb Paul, S. Bhunia
IOLock: An Input/Output Locking Scheme for Chip and PCB Protection against Reverse-Engineering Attacks
C. Vega, P. SLPSK, S. Bhunia
FLEX PUF: A Flexible Physical Unclonable Function Design Using Configurable Templates
C. Vega, P. SLPSK, A. Chatterjee, S. Bhunia
Resource-efficient PUF Implementation Through FPGA Resource Re-utilization
C. Vega
VARI-CHECK: Authentication of COTS Devices using ML-Based Variability Characterization
C. Vega, P. SLPSK, R. Karnati, S. Bhunia
Get in touch.
If you have any question or inquiries please feel free to send me an email.
- chrisvega@cvega.app
- Location
- Bay Area, California
- Chris Vega
- Github
- ChrisVega